Identifying the Clocks Related to Each Port - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Before defining the I/O delay constraint, you must identify which clocks are related to each port. You can identify the clocks using the methods described in the following sections.