Using Gated Clocks - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

AMD devices include dedicated clock networks that can provide a large-fanout, low-skew clocking resource. Fine-grained clock gating techniques included in the HDL code can disrupt the functionality and prevent efficient use of the dedicated clocking resources. Therefore, when writing HDL to target a device, AMD does not recommend that you code clock gating constructs into the clock path. Instead, control clocking by using coding techniques to infer clock enables to stop portions of the design, either for functionality or power reasons.