Gating the Clock Buffer - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

When larger portions of the clock network can be shut down for periods of time, you can enable or disable the clock network using a BUFGCE or BUFGCTRL. In addition, when targeting UltraScale devices, you can gate the BUFGCE_DIV and BUFG_GT. For 7 series devices, you can also use the BUFHCE, BUFR, and BUFMRCE to gate the clock.

When a clock can be slowed down during periods of time, you can also use these buffers with additional logic to periodically enable the clock net. Alternatively, you can use a BUFGMUX or BUFGCTRL to switch the clock source from a faster clock signal to a slower clock.

Any of these techniques can effectively reduce dynamic power. However, depending on the requirements and clock topology, one technique may prove more effective than another. For example, in 7 series devices:

  • A BUFR might work best if it is an externally generated clock (under 450 MHz) that is only needed to source up to three clock regions.
  • For Virtex 7 devices, a BUFMRCE might also be needed to use this technique with more than one clock region (but only up to three vertically adjacent regions).
  • A BUFHCE is better suited for higher-speed clocks that can be contained in a single clock region. Although a BUFGCE may span the device and is the most flexible approach, it might not be the best choice for the greatest power savings.