Optimize Hierarchy for Advanced Design Techniques - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

Advanced design techniques such as bottom-up synthesis, Dynamic Function eXchange (DFX), and out-of-context design require planning at the hierarchical level. The designer must choose the appropriate level of hierarchy for the technique being used. These techniques are not covered in this document.