Pre- and Post-Physical Optimization - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Evaluate the need for running physical optimization to fix timing problems related to:

  • Nets with high fanout (report_high_fanout_nets shows highest fanout non-clock nets)
  • Nets with drivers and loads located far apart
  • Digital signal processor (DSP) and block RAM with sub-optimal pipeline register usage