Follow Control Set Guidelines - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The following table provides a guideline for the recommended number of control sets, depending on the target device size, for both 7 series and UltraScale devices.

Table 1. Control Set Guidelines
Guideline Percentage of Control Sets
Acceptable Less than 7.5% of the total number of control sets in the device
Reduction Recommended Between 7.5% and 15% of the total number of control sets in the device
Reduction Required Greater than 15% of the total number of control sets in the device

These guidelines assume the following:

  • Typical control set capacity: 1 per 8 CLB registers
  • Total number of control sets in a device: CLB registers / 8

To determine the number of control sets in a design:

  • Before placement: Use report_control_sets -verbose
  • After placement: Use report_utilization (text mode only)
Tip: The number of unique control sets can be a problem in a small portion of the design, resulting in longer net delays or congestion in the corresponding device area. Identifying the high local density of unique control sets requires detailed placement analysis in the Vivado IDE Device window, which includes highlighted control signals in different colors.