Improving the Netlist with Block-Level Synthesis Strategies - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Although most designs can meet timing requirements with the default Vivado synthesis settings, larger and more complex designs usually require a mix of synthesis strategies for different hierarchies to close timing.

For example, one module might require the use of MUXF* resources to implement a timing critical function, but the rest of the design might benefit from implementation of logic in LUTs rather than MUXF* to reduce congestion. In this case, set the PERFORMANCE_OPTIMIZED strategy for the timing-critical module, and synthesize the rest of the design using the Flow_AlternateRoutability strategy to reduce congestion.