Datapath Delay and Logic Levels - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

In general, the number of LUTs and other primitives in the path is most important factor in contributing to the delay. Because LUT delays are reported differently in different devices, separate cell delay and route delay ranges must be considered.

If the path delay is dominated by:

  • Cell delay is >25% in 7 series devices and >50% in UltraScale devices.

    Can the path be modified to be shorter or to use faster logic cells? See Reducing Logic Delay.

  • Route delay is >75% in 7 series devices and >50% in UltraScale devices.

    Was this path impacted by hold fixing? You can determine this by running report_design_analysis -show_all and examining the Hold Detour column. Use the corresponding analysis technique.

    • Yes - Is the impacted net part of a CDC path?
      • Yes - Is the CDC path missing a constraint?
      • No - Do the startpoint and endpoint of that hold-fixed path use a balanced clock tree? Look at the skew value.
    • No - See the following information on congestion.

    Was this path impacted by congestion? Look at each individual net delay, the fanout and observe the routing in the Device view with routing details enabled (post-route analysis only). You can also turn on the congestion metrics to see if the path is located in or near a congested area. Use the following analysis steps for a quick assessment or review Reducing Net Delay Caused by Congestion for a comprehensive analysis.

    • Yes - For the nets with the highest delay value, is the fanout low (<10)?
      • Yes - If the routing seems optimal (straight line) but driver and load are far apart, the sub-optimal placement is related to congestion. Review Addressing Congestion to identify the best resolution technique.
      • No - Try to use physical logic optimization to duplicate the driver of the net. Once duplicated, each driver can automatically be placed closer to its loads, which will reduce the overall datapath delay. Review Optimizing High Fanout Nets for more details and to learn about alternate techniques.
    • No - The design is spread out too much. Try one of the following techniques to improve the placement: