Impact on Synthesis and Implementation - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The set_multicycle_path constraint is supported by synthesis and can greatly improve the timing QoR (for setup only) by relaxing long paths that are functionally not active at every clock cycle.

As for synthesis, multicycle path exceptions help the implementation timing-driven algorithms to focus on the real critical paths. The hold requirements are important only during routing. If a setup relationship was adjusted with a set_multicycle_path constraint but not its corresponding hold relationships, the worst hold requirement may become too hard to meet if it is over 2 or 3 ns. This situation can have a negative impact on setup slack because of the additional delay inserted by the router while fixing hold violations.