Running RTL DRCs - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

A set of RTL DRC rules identify potential coding issues with your HDL. You can perform these checks on the elaborated views, which you can open by clicking Open Elaborated Design in the Flow Navigator. You can run these DRC checks by selecting RTL Analysis > Report Methodology in the Flow Navigator or by executing report_methodology at the Tcl command prompt.