Resource Planning within SLR0 - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

Proper management of the HBM AXI Interfaces and other logic within the SLR0 can provide optimal quality of results (QoR) and minimize routing congestion. Following are some common design planning considerations for the SLR0 in HBM devices:

  • For designs that heavily utilize the HBM AXI interfaces, budget for lower overall fabric utilization of non-HBM logic in SLR0 to better accommodate the resources required for the HBM AXI interfaces.
  • Using MIG IP in the SLR0 might result in timing closure challenges for HBM AXI interfaces located near the I/O columns of the device. When using MIG IP, consider using the I/O columns located in SLR2 or SLR1.
  • Be aware of address ranges and the physical location of the HBM AXI interfaces that can impact the latency and bandwidth of the design. To optimize the performance of the HBM, utilize the physical HBM AXI interfaces on the same device side as the addressed HBM stack.