Checking for Positive Timing Slacks - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The following timing metrics reflect the design timing score. Numbers must be positive to meet timing.

  • Setup/Recovery (max delay analysis): WNS > 0 ns and TNS = 0 ns
  • Hold/Removal (min delay analysis): WHS > 0 ns and THS = 0 ns
  • Pulse Width: WPWS > 0 ns and TPWS = 0 ns