Netlist-Based I/O Planning - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The recommended time in the design cycle to assign I/Os and clock logic constraints is after the design has been synthesized. The clock logic paths are established in the netlist for constraint assignment purposes. The I/O and clock logic DRCs are also more comprehensive.

See the 7 Series FPGAs PCB Design Guide (UG483), UltraScale Architecture PCB Design User Guide (UG583), or Zynq 7000 SoC PCB Design Guide (UG933) to ensure proper I/O configuration for your device. For more information, see this link in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).