Defining Physical Constraints - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

Physical constraints are used to control floorplan, specific placement, I/O assignments, routers and similar functions. Make sure that each pin has an I/O location and standard specified. Physical constraints are covered in the following user guides:

  • For locking placement and routing, including relative placement of macros, see the Vivado Design Suite User Guide: Using Constraints (UG903).
  • For floorplanning, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
  • For configuration, see the Vivado Design Suite User Guide: Programming and Debugging (UG908).