Use of IP - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Certain IP assists in the creation of the clocking structures. Clocking Wizard and IO Wizard specifically can assist in the selection and creation of the clocking resources and structure, including:

  • BUFG
  • BUFGCE
  • BUFGCE_DIV (UltraScale devices)
  • BUFGCTRL
  • BUFIO (7 series devices)
  • BUFR (7 series devices)
  • Clock modifying blocks such as:
    • Mixed Mode Clocking Manager (MMCM)
    • Phase-locked loop (PLL) components

More complex IP, such as PCIe or Transceivers Wizard IP, might also include clocking structures as part of the overall IP. This might provide additional clocking resources if properly taken into account. If not taken into account, it might limit some clocking options for the remainder of the design.

AMD highly recommends that, for any instantiated IP, the clocking requirements, capabilities, and resources are well understood and leveraged where possible in other portions of the design.