Timing constraints between different clocks are permitted. These paths are timed by default. If the paths are valid, ensure the clocks are truly synchronous and share a common source. You must also verify that the paths requirement between these clocks does not introduce tighter requirements than needed for the design to be functional in hardware.
For paths between different clocks that are not valid timing paths, you
must use set_clock_groups or set_false_path between the clocks on these paths. Any time that you use
timing exceptions, you must ensure that they affect only the intended paths. Review the
Clock Interaction Report to ensure inter-clock paths are constrained properly.