VIO Core Considerations - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

When using VIO cores, consider the following:

  • Signals connected to VIO input probes must be synchronous to the clock connected to the VIO clk port on the VIO core. Connecting signals that are not synchronous to the clk port results in a clock domain crossing at the VIO input probe port.
  • Signals driven from VIO output probes are asserted and deasserted synchronous to the clock connected to the VIO clk port on the VIO core.
  • The VIO core has a relatively low refresh rate because it is intended to replace low speed board I/O, such as push-buttons or light-emitting diodes (LEDs). To capture high-speed signals, consider using the ILA core.