Congestion in the Placer Log - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The placer estimates congestion throughout the placement phases and spreads the logic in congested areas. This helps reducing the interconnect utilization to improve routability, and also the estimated versus routed delays correlation. However, when the congestion cannot be reduced due to high utilization or other reasons, the placer does not print congestion details but issues the following warning:

WARNING: [Place 46-14] The placer has determined that this design is highly congested 
and may have difficulty routing. Run report_design_analysis -congestion for a 
detailed report.

In that case the QoR is very likely impacted and it is prudent to address the issues causing the congestion before continuing on to the router. As stated in the message, use the report_design_analysis command to report the actual congestion levels, as well as identify their location and the logic placed in the same area.