Inferring RAM and ROM - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

RAM and ROM may be specified in multiple ways. Each has advantages and disadvantages.

  • Inference

    Advantages:

    • Highly portable
    • Easy to read and understand
    • Self-documenting
    • Fast simulation

    Disadvantages:

    • Might not have access to all RAM configurations available
    • Might produce less optimal results

    Because inference usually gives good results, it is the recommended method, unless a given use is not supported, or it is not producing adequate results in achievable clock frequency, area, or power. In that case, explore other methods.

    When inferring RAM, AMD recommends that you use the HDL Templates provided in the Vivado tools. As mentioned earlier, using asynchronous reset impacts RAM inference, and should be avoided.

  • Xilinx Parameterizable Macros (XPMs)

    Advantages:

    • Portable between AMD device families
    • Fast simulation
    • Support for asymmetric width
    • Predictable quality of results (QoR)

    Disadvantages:

    • Limited to supported XPM options

    XPMs are built on inference using fixed templates that you cannot modify. Therefore, they can guarantee QoR and can support features that standard inference does not. When standard inference does not support the features required, AMD recommends you use XPMs instead.

    Note: When you compile simulation libraries using compile_simlib, XPMs are automatically compiled. For more information, see the Vivado Design Suite User Guide: Logic Simulation (UG900).
  • Direct Instantiation of RAM Primitives

    Advantages:

    • Highest level control over implementation
    • Access to all capabilities of the block

    Disadvantages:

    • Less portable code
    • Wordier and more difficult to understand functionality and intent
  • Core from IP catalog

    Advantages:

    • Generally more optimized result when using multiple components
    • Simple to specify and configure

    Disadvantages:

    • Less portable code
    • Core management