Incremental Synthesis - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

You can use incremental synthesis to reuse existing synthesis results. This approach reduces typical synthesis compile times by 50%. When used with the incremental implementation flow, this approach also improves overall compile time and timing closure consistency.

When a design is synthesized, it is broken into RTL partitions. Incremental synthesis reuses RTL partitions from a previous synthesis run. RTL partitions are typically created along logical hierarchies. Incremental synthesis only runs if the design is large enough that synthesis creates at least four RTL partitions, each containing at least 50000 instances. Instances include both logical hierarchy and RTL primitives.

Following are the different modes available when using the synth_design -incremental_mode <value> command:

off
Incremental synthesis is not run.
quick
Fastest results but no cross boundary optimizations. This mode limits logic operating frequency.
default
Most logic optimizations enabled, including cross-boundary optimization. Compile time is significantly reduced from non-incremental synthesis.
aggressive
All optimizations are enabled. Compile time is significantly reduced from non-incremental synthesis.

The quick mode is typically recommended for low-performance designs only. Without cross boundary optimizations, typical designs have reduced clock frequency. However, if a design is well constructed with registered hierarchical boundaries, achievable clock frequency might not be affected. Due to the limits on cross-boundary optimization, resynthesis in a given area is caused by RTL changes only in that area. Changes in another synthesis partition do not trigger changes beyond that partition. This leads to more reuse and a faster synthesis result. For other modes, this is not the case, and RTL changes might trigger the resynthesis of more partitions beyond just the partition the cell is in. When more than 50% of partitions are modified, a full resynthesis is triggered.

For high-performance designs, the default, aggressive, and off modes are recommended. More optimizations are enabled in aggressive and off modes, which might lead to more resynthesis but higher QoR.

To more aggressively address compile time concerns, you can compare the incremental synthesis against OOC synthesis. OOC synthesis is typically used by IP, and setup is automatic. Global synthesis with incremental synthesis offers the advantage of cross-boundary optimizations as well as compile time benefits. Following are areas to consider:

  • Compile time

    OOC synthesis is faster, because it reduces the amount of code that is elaborated each time. RTL is only elaborated if the RTL is modified within the OOC module.

  • Performance

    Incremental synthesis has a maximum clock frequency advantage over OOC synthesis, because this mode allows optimizations across OOC boundaries.

  • Setup

    For non-IP flows, when you create an OOC synthesis run, you must create a wrapper when generics/parameters are passed from higher modules. In addition, you must create a separate timing constraint file to target the OOC-level ports. Incremental synthesis does not have these requirements.

For more information, see the Vivado Design Suite User Guide: Synthesis (UG901).