Connecting a Net to a Free External Pin Using Post-Route ECO - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

In some cases you might want to bring a net out to a free device pin for debug using external test equipment. This approach can be useful if you are debugging issues that require minimal changes to the design QoR or require measurements not possible to obtain through other means. You can do this by using the Engineering Change Order (ECO) flow as long as the device has an unused I/O that can be used for this purpose. For more information on using the ECO flow to modify a routed design, see this link in the Vivado Design Suite User Guide: Implementation (UG904).