Clocking Recommendations for Platforms and Dynamic Function eXchange - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

This section covers the clocking guidelines for Dynamic Function eXchange (DFX) designs. In general, clocks in a DFX design are categorized as internal clocks and boundary clocks:

Reconfigurable module internal clocks
Clocks with driver and all loads inside the reconfigurable module (RM).
Boundary clocks
Clocks with nets crossing the cell boundary of the reconfigurable module as follows:
  • Driver in the static region and loads in the RM
  • Driver in the RM and loads in the static region
  • Driver in the static region and loads distributed between RM and static region
  • Driver in the RM region and loads distributed between RM and static region

The following figure shows an example of the different boundary clocks.

Figure 1. DFX Clock Tile Sharing

For more information on DFX, see the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).