Specifying Timing Exceptions - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Timing exceptions are used to modify how timing analysis is done on specific paths. By default, the timing engine assumes that all paths should be timed with a single cycle requirement for setup analysis to cover the most pessimistic clocking scenario. For certain paths, this is not true. Following are a few examples:

  • Asynchronous CDC paths cannot be safely timed due to the lack of fixed phase relationship between the clocks. They should be ignored (Clock Groups, False Path), or simply have datapath delay constraint (Max Delay Datapath Only)
  • The sequential cells launch and capture edges are not active at every clock cycle, so the path requirement can be relaxed accordingly (Multicycle Path)
  • The path delay requirement needs to be tightened to increase the design margin in hardware (Max Delay)
  • A path through a combinatorial cell is static and does not need to be timed (False Path, Case Analysis)
  • The analysis should be done with only a particular clock driven by a multiplexer (Case Analysis).

In any case, timing exceptions must be used carefully and must not be added to hide real timing problems.