7 Series Device Clocking - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English
Note: This section uses AMD Virtex™ 7 clocking resources as an example. The clocking resources for Virtex-6 devices are similar. If you are using a different architecture, see the 7 Series FPGAs Clocking Resources User Guide (UG472) or the UltraScale Architecture Clocking Resources User Guide (UG572) depending on your device.

Virtex-6 and Virtex 7 devices contain thirty-two global clock buffers known as BUFGs. BUFGs can serve most clocking needs for designs with less demanding needs in terms of number of clocks, design performance, and clocking control. Global clocking resources include BUFG, BUFGCE, BUFGMUX, and BUFGCTRL primitives, which each have their own features. For more information on the features of these global clock components, see the Clocking Resources Guide ( 7 Series FPGAs Clocking Resources User Guide (UG472) or UltraScale Architecture Clocking Resources User Guide (UG572)) and Libraries Guide ( Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953) or UltraScale Architecture Libraries Guide (UG974)) for your device.

In addition to global clocking resources, regional clocking resources are also available, which allow tighter control of clock networks. Regional clocking resources include the Horizontal Clock Region Buffers (BUFH, BUFHCE), Regional Clock Buffer (BUFR), I/O Clock Buffer (BUFIO), and Multi-Regional Clock Buffer (BUFMR). For more information on the features of these regional clock components, see the Clocking Resources Guide ( 7 Series FPGAs Clocking Resources User Guide (UG472) or UltraScale Architecture Clocking Resources User Guide (UG572)) and Libraries Guide ( Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953) or UltraScale Architecture Libraries Guide (UG974)) for your device.