Methodology DRCs with Impact on Timing Closure - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The DRCs shown in the following table flag design and timing constraint combinations that increase the stress on implementation tools, leading to impossible or inconsistent timing closure. These DRCs usually point to missing clock domain crossing (CDC) constraints, inappropriate clock trees, or inconsistent timing exception coverage due to logic replication. They must be addressed with highest priority.

Important: Carefully verify timing checks with a severity of Critical Warning.

For more information on timing methodology checks, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Table 1. Timing Closure Methodology DRCs
Check Severity Description
TIMING-6 Critical Warning No common clock between related clocks
TIMING-7 Critical Warning No common node between related clocks
TIMING-8 Critical Warning No common period between related clocks
TIMING-14 Critical Warning LUT on the clock tree
TIMING-15 Warning Large hold violation on inter-clock path
TIMING-16 Warning Large setup violation
TIMING-30 Warning Sub-optimal master source pin selection for generated clock
TIMING-31 Critical Warning Inappropriate multicycle path between phase shifted clocks
TIMING-32, TIMING-33, TIMING-34, TIMING-37, TIMING-38, TIMING-39 Warning Non-recommended bus skew constraint
TIMING-36 Critical Warning Missing master clock edge propagation for generated clock
TIMING-42 Warning Clock propagation prevented by path segmentation
TIMING-44

TIMING-45

Warning Unreasonable user intra and inter-clock uncertainty
TIMING-48 Advisory Max Delay Datapath Only constraint on latch input
TIMING-49 Critical Warning Unsafe enable or reset topology from parallel BUFGCE_DIV
TIMING-50 Warning Unrealistic path requirement between same-level latches
TIMING-56 Warning Missing logically or physically excluded clock groups constraint
XDCB-3 Warning Same clock mentioned in multiple groups in the same set_clock_groups command
XDCH-1 Warning Hold option missing in multicycle path constraint
XDCV-1 Warning Incomplete constraint coverage due to missing original object used in replication
XDCV-2 Warning Incomplete constraint coverage due to missing replicated objects