Further Refining Control Signal Activity After Running Power Analysis - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

When SAIF-based annotation has not been used for accurate power analysis, you can fine-tune the power analysis after doing the first level analysis. For more information, see this link in the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).