Check Timing Report - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

The Check Timing report (multiple_clock) identifies the clock pins that are reached by more than one clock and a set_clock_groups or set_false_path constraint has not already been defined between these clocks.