High Fanouts in Critical Paths - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2024.1 English
High fanout nets are much easier to deal with early in the design process. What constitutes too high of a fanout is often dictated by the target clock frequency requirements and the construction of the paths. You can use the following techniques to address issues with high fanout nets.