PCB Design Considerations - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English
The PCB should be designed considering the fastest signal interfacing with the device. These high-speed signals are extremely sensitive to trace geometry, vias, loss, and crosstalk. These aspects become even more prominent for multi-layer PCBs. For high-speed interfaces perform a signal integrity simulation. A board redesign with improved PCB material or altered trace geometries might be necessary to obtain the desired performance.

AMD recommends following these steps when designing your PCB:

  1. Review the following device documentation:
    • PCB Design Guide for your device.
    • Board design guidelines in the transceiver user guide for your device.
  2. Review memory IP and PCIe® design guidelines in the IP product guides.
  3. Use the Vivado tools to validate your I/O planning:
    • Run simultaneous switching noise (SSN) analysis.
    • Run built-in DRCs.
    • Export I/O buffer information specification (IBIS) models.
  4. Run signal integrity analysis as follows:
    • For gigabit transceivers (GTs), run Spice or IBIS-AMI simulations using channel parameters.
    • For lower performance interfaces, run IBIS simulation to check for issues with overshoot or undershoot.
  5. Use the Xilinx Power Estimator (XPE) or Power Design Manager (PDM) tool (download at www.amd.com/power) with Process set to Maximum to generate an early estimate of the power consumption for the design.
  6. Complete and adhere to the schematic checklist for your device.
    Note: See the 7 Series Schematic Review Recommendations (XMP277), Kintex UltraScale and Virtex UltraScale FPGAs Schematic Review Checklist (XTP344), or UltraScale+ FPGAs and Zynq Ultrascale+ Devices Schematic Review Checklist (XTP427).
  7. Manually add XDC operating condition constraints to your XDC file for the Vivado tools.Use the XPE or PDM tool to generate a Xilinx design constraints (XDC) file, and import this file into the corresponding Vivado project. The XPE and PDM tool environment settings are translated to XDC constraints. The estimated total on-chip power becomes the design power budget for Vivado power analysis. For more information, see the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).