Clock Skew and Uncertainty - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

AMD devices use various types of routing resources to support most common clocking schemes and requirements such as high fanout clocks, short propagation delays, and extremely low skew. Clock skew affects any register-to-register path with either combinational logic or interconnect between them.

Clock skew in high frequency clock domains (+300 MHz) can impact performance. In general, the clock skew should be no more than 500 ps. For example, 500 ps represents 15% of a 300 MHz clock period, which is equivalent to the timing budget of 1 or 2 logic levels. In clock domain-crossing paths the skew can be higher, because the clocks use different resources and the common node is located further up the clock trees. SDC-based tools analyze timing between all clock groups unless timing exception constraints specify that they should not be (for example, set_clock_groups, set_false_path, or set_max_delay -datapath_only).

If the clock uncertainty is over 100 ps, then you must review the clock topology and jitter numbers to understand why the uncertainty is so high.