Using Hard SLR Floorplan Constraints - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

For high-performance designs, sufficient pipelining between the major hierarchies is required to ease global placement and SLR partitioning. When a design is challenging, SLR crossing points can change from run to run. In addition to defining SLR Pblocks, you can create additional Pblocks that are aligned to clock regions and located along the SLR boundary to constrain the crossing flip-flops. The following example shows an UltraScale ku115 SSI device with the following Pblocks:

  • 2 SLR Pblocks: SLR0 and SLR1
  • 2 SLR-crossing Pblocks: SLR0_top_row and SLR1_bottom_row
    Figure 1. SLR-Crossing Pblock Example

    Important: AMD recommends using CLOCKREGION ranges instead of LAGUNA ranges for SLR-crossing Pblocks.
    Tip: You can define SLR Pblocks by specifying a complete SLR. For example, resize_pblock pblock_SLR0 -add SLR0.

For more information, see this link in Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

Video: For information on using floorplanning techniques to address design timing closure issues, see the Vivado Design Suite QuickTake Video: Design Analysis and Floorplanning.