Understanding Timing Reports - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The Timing Summary report provides high-level information on the timing characteristics of the design compared to the constraints provided. Review the timing summary numbers during signoff:

Total Negative Slack (TNS)
The sum of the setup/recovery violations for each endpoint in the entire design or for a particular clock domain. The worst setup/recovery slack is the worst negative slack (WNS).
Total Hold Slack (THS)
The sum of the hold/removal violations for each endpoint in the entire design or for a particular clock domain. The worst hold/removal slack is the worst hold slack (WHS).
Total Pulse Width Slack (TPWS)
The sum of the violations for each clock pin in the entire design or a particular clock domain for the following checks:
  • Minimum low pulse width
  • Minimum high pulse width
  • Minimum period
  • Maximum period
  • Maximum skew (between two clock pins of a same leaf cell)
Worst Pulse Width Slack (WPWS)
The worst slack for all pulse width, period, or skew checks on any given clock pin.

The Total Slack (TNS, THS or TPWS) only reflects the violations in the design. When all timing checks are met, the Total Slack is null.

The timing path report provides detailed information on how the slack is computed on any logical path for any timing check. In a fully constrained design, each path has one or several requirements that must all be met in order for the associated logic to function reliably.

The main checks covered by WNS, TNS, WHS, and THS are derived from the sequential cell functional requirements:

Setup time
The time before which the new stable data must be available before the next active clock edge to be safely captured.
Hold requirement
The amount of time the data must remain stable after an active clock edge to avoid capturing an undesired value.
Recovery time
The minimum time required between the time the asynchronous reset signal has toggled to its inactive state and the next active clock edge.
Removal time
The minimum time after an active clock edge before the asynchronous reset signal can be safely toggled to its inactive state.

A simple example is a path between two flip-flops that are connected to the same clock net.

After a timing clock is defined on the clock net, the timing analysis performs both setup and hold checks at the data pin of the destination flip-flop under the most pessimistic, but reasonable, operating conditions. The data transfer from the source flip-flop to the destination flip-flop occurs safely when both setup and hold slacks are positive.

For more information on timing analysis, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).