Analyze Path Characteristics - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

To report the 50 worst setup timing paths, you can use the Report Design Analysis dialog box in the Vivado IDE, or you can use the following command:

report_design_analysis -max_paths 50 -setup -name design_analysis_postRoute

The following figure shows an example of the Setup Path Characteristics table generated by this command. To see additional columns in the window, scroll horizontally.

Figure 1. Report Design Analysis Timing Path Characteristics Post-Route

Following are tips for working with this table:

  • Toggle between numbers and % by clicking the % (Show Percentage) button. This is particularly helpful to review proportion of cell delay and net delay.
  • By default, columns with only null or empty values are hidden. Click the Hide Unused button to turn off filtering and show all columns, or right-click the table header to select which columns to show or hide.

From this table, you can isolate which characteristics are introducing the timing violation for each path:

Note: The relevant table column is shown in parentheses below.
  • High logic delay percentage (Logic Delay)
    • Are there many levels of logic? (Logic Levels)
    • Are there any constraints or attributes that prevent logic optimization? (DONT_TOUCH, MARK_DEBUG)
    • Does the path include a cell with high logic delay such as block RAM or DSP? (Logical Path, Start Point Pin Primitive, End Point Pin Primitive)
    • Is the path requirement too tight for the current path topology? (Requirement)
  • High net delay percentage (Net Delay)
    • Are there any high fanout nets in the path? (High Fanout, Cumulative Fanout)
    • Are the cells assigned to several Pblocks that can be placed far apart? (Pblocks)
    • Are the cells placed far apart? (Bounding Box Size, Clock Region Distance)
    • For SSI technology devices, are there nets crossing SLR boundaries? (SLR Crossings)
    • Are one or several net delay values a lot higher than expected while the placement seems correct? Select the path and visualize its placement and routing in the Device window.
    • Is there a missing pipeline register in a block RAM or DSP cell? (Comb DSP, MREG, PREG, DOA_REG, DOB_REG)
  • High skew <-0.5 ns for setup and >0.5 ns for hold (Clock Skew)
    • Is it a clock domain crossing path? (Start Point Clock, End Point Clock)
    • Are the clocks synchronous or asynchronous? (Clock Relationship)
    • Is the path crossing I/O columns? (IO Crossings)
    Tip: For visualizing the details of the timing paths in the Vivado IDE, select the path in the table, and go to the Properties tab.