Timing Exceptions Guidelines - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Use a limited number of timing exceptions and keep them simple whenever possible. Otherwise, you will face the following challenges:

  • The implementation compile time significantly increases when many exceptions are used, especially when they are attached to a large number of netlist objects.
  • Constraints debugging becomes extremely complicated when several exceptions cover the same paths.
  • Presence of constraints on a signal can hamper the optimization of that signal. Therefore, including unnecessary exceptions or unnecessary points in exception commands can hamper optimization.

Following is an example of timing exceptions that can negatively impact the run time:

set_false_path -from [get_ports din] -to [all_registers]
  • If the din port does not have an input delay, it is not constrained. So there is no need to add a false path.
  • If the din port feeds only to sequential elements, there is no need to specify the false path to the sequential cells explicitly. This constraint can be written more efficiently:
    set_false_path -from [get_ports din]
  • If the false path is needed, but only a few paths exist from the din port to any sequential cell in the design, then it can be more specific (all_registers can potentially return thousands of cells, depending upon the number of registers used in the design):
    set_false_path -from [get_ports din] -to [get_cells blockA/config_reg[*]]