Jitter - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

For jitter, it is best to use the default values used by the Vivado Design Suite. You can modify the default computation as follows:

  • If a primary clock enters the device with a random jitter greater than zero, use the set_input_jitter command to specify the peak-to-peak jitter value in nanoseconds.
  • To adjust the global jitter if the device power supply is noisy, use set_system_jitter. AMD does not recommend increasing the default system jitter value.

For generated clocks, the jitter is derived from the master clock and the characteristics of the clock modifying block. You do not need to adjust these numbers.