The Vivado IDE allows you to interactively explore, visualize, assign, and validate the I/O ports and clock logic in your design. The environment ensures correct-by-construction I/O assignment. It also provides visualization of the external package pins in correlation with the internal die pads.
You can visualize the data flow through the device and properly plan I/Os from both an external and internal perspective. After the I/Os are assigned and configured through the Vivado IDE, constraints are then automatically created for the implementation tools.
For more information on Vivado Design Suite I/O and clock planning capabilities, see the following resources:
- Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
- Vivado Design Suite QuickTake Video: I/O Planning Overview