Valid Startpoints and Endpoints - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Path segmentation is reported by the tools in the log file when the constraints are applied. You must avoid it by using valid startpoints and endpoints:

Startpoints
Clock, clock pin, sequential cell (implies valid startpoint pins of the cell), input or inout port.
Endpoints
Clock, input data pin of sequential cell, sequential cell (implies valid endpoint pins of the cell), output or inout port.

For details on path segmentation, see this link in the Vivado Design Suite User Guide: Using Constraints (UG903).