Checking That Your Design is Properly Constrained - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Before looking at the timing results to see if there are any violations, be sure that every synchronous endpoint in your design is properly constrained.

Run check_timing to identify unconstrained paths. You can run this command as a standalone command, but it is also part of report_timing_summary. In addition, report_timing_summary includes an Unconstrained Paths section where N logical paths without timing requirements are listed by the already defined source or destination timing clock. N is controlled by the -max_path option.

After the design is fully constrained, run the report_methodology command and review the TIMING and XDC checks to identify non-optimal constraints, which will likely make timing analysis not fully accurate and lead to timing margin variations in hardware. To identify and correct unrealistic target clock frequencies or setup path requirement, use the report_qor_assessment command.

Important: To address missing or incomplete constraints, use the Timing Constraints wizard or see the Vivado Design Suite User Guide: Using Constraints (UG903).