Pre-RTL I/O Planning - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

If your design cycle forces you to define the I/O configuration before you have a synthesized netlist, take great care to ensure adherence to all relevant rules. The Vivado tools include a Pin Planning Project environment that allows you to import I/O definitions using a CSV or XDC format file. You can also create a dummy RTL with just the port directions defined. Availability of port direction makes SSN analysis more accurate as input and output signals have different contributions to SSN.

I/O ports can also be created and configured interactively. Basic I/O bank DRC rules are provided.

See the 7 Series FPGAs PCB Design Guide (UG483), UltraScale Architecture PCB Design User Guide (UG583), or Zynq 7000 SoC PCB Design Guide (UG933) to ensure proper I/O configuration for your device. For more information, see this link in the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).