Identifying Clock Pairs without Common Primary Clocks - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The clock interaction report indicates whether or not each pair of interacting clocks has a common primary clock source. Clock pairs that do not share a common primary clock are frequently asynchronous to each other. Therefore, it is helpful to identify these pairs by sorting the columns in the report using the Common Primary Clock field. The report does not determine whether clock-domain crossing paths are or are not designed properly.

Use the report_cdc Tcl command for a comprehensive analysis of clock domain crossing circuitry between asynchronous clocks. For more information on the report_cdc command, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906). Also, see report_cdc in the Vivado Design Suite Tcl Command Reference Guide (UG835).