Following Guidelines to Address Remaining Violations - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English
Important: Analyze timing post-synthesis to identify the major design issues that must be resolved before you move forward in the flow.

HDL changes tend to have the biggest impact on QoR. You are therefore better off solving problems before implementation to achieve faster timing convergence. When analyzing timing paths, pay special attention to the following:

  • Most frequent offenders (that is, the cells or nets that show up the most in the top worst failing timing paths)
  • Paths sourced by unregistered block RAMs
  • Paths sourced by SRL
  • Paths containing unregistered, cascaded DSP blocks
  • Paths with large number of logic levels
  • Paths with large fanout