Parallel Runs - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

To improve your chances of meeting timing using the default flow, it is common to implement many parallel runs, each with different placer directives. For incremental flows, the directive indicates whether to close or maintain timing. To achieve a spread of results, target the desired incremental directive with different reference checkpoints.