I/O Timing with MMCM ZHOLD/BUF_IN Compensation - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

ZHOLD compensation indicates that the MMCM is configured to provide a negative hold for all I/O registers of an entire I/O column. When a clock capable I/O (CCIO) drives a single MMCM that is configured in ZHOLD compensation mode, the placer will attempt to place the MMCM with the CCIO in the same clock region. In this case, the CCIO can drive the MMCM directly without going through a BUFG. This allows the ZHOLD compensation of the MMCM to remain in effect.

However, if a CCIO drives an MMCM configured in ZHOLD mode in addition to another MMCM, logic optimization will attempt to legalize the clock routing to the MMCMs by inserting a BUFG after the CCIO. Because the MMCM with ZHOLD compensation is no longer driven directly by a CCIO, the compensation is changed to BUF_IN. To avoid this, ensure that the CCIO drives the MMCM configured in ZHOLD mode directly and drives the additional MMCM through a BUFG. In addition, set the CLOCK_DEDICATED_ROUTE property for the net driven by the BUFG to ANY_CMT_COLUMN.

Because the clock insertion delay varies with the clock root locations and the clock root placement depends on placement of the loads, there might be variability between runs. This variability affects the timing inside the device as well as the I/O timing.

When dealing with high-frequency I/Os, you might want more control over the I/O timing and less variability between runs. One way to achieve this is to force the clock root placement. You can run the tool in automated mode and look at the clock root region. If the I/O timing is satisfactory, you can force the clock root placement on the buffer nets associated with I/O timing. To determine the placement of the clock roots, use the report_clock_utilization [-clock_roots_only] Tcl command.

In the following example, the I/O ports are located in the X0Y0 region. The Vivado placer determined the placement of the clock roots in X1Y2 based on the I/O placement as well as placement of other loads.

Figure 1. Clock Utilization Summary with Unconstrained Clock Root

The following summary shows the I/O timing when the clock root is unconstrained.

Figure 2. Timing Summary with Unconstrained Clock Root

In the following example, the clock roots are moved next to the I/O registers in X0Y0, which reduces the clock insertion delays and timing pessimism and therefore, improves the I/O timing.

Figure 3. Clock Utilization Summary with User Constrained Clock Root

The following summary shows the I/O timing when the clock root is moved.

Figure 4. Timing Summary with User Constrained Clock Root