Global Synthesis - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

In the global synthesis flow, the full design is synthesized in one run, which offers the following advantages:

  • Allows the synthesis tool to perform the maximum optimization. Because the synthesis tool is aware of the full design, the tool can optimize between hierarchies that other flows might not.
  • Enables easy analysis after the synthesis run.

The disadvantage of this flow is longer compile time. Every time synthesis is run, the full design is rerun. However, this disadvantage can be mitigated by using incremental synthesis.

Note: If your design includes XDC constraints, you must reference the objects to the top-level design.