Fast PCI Express endpoint enumeration
using tandem configuration is not supported. This use case addresses the ability to initially
load a fully configurable PCI Express protocol solution
from a small external ROM, so as to meet the 100 ms enumeration requirement. Support for
tandem configuration for the PL PCIE block in AMD
Versal adaptive SoC is not currently planned.
Note: This IP architecture assumes exclusive use of one or more complete GT
quads, regardless of the designed link width. While it might be possible to share unused
lanes in the GT quad with other instances of this IP, non-PCIe IPs, or custom GT-based
interfaces for x2 and x1 link widths. AMD does not support evaluations or
implementations of such sharing arrangements. The feasibility of sharing depends on the
specific GT configuration required for other protocols, links, and lanes intended to share
the GT quad. Factors affecting GT configuration include external REFCLKs, fabric design
clocks and resets, GT clock management resources, connectivity rules, mode, and electrical
settings.
Note: Any user design
requiring fast PCIe enumeration or configuration through
PCIe should use the PCIe controllers in the CPM. Not all AMD
Versal adaptive SoCs contain this particular resource.
For details, see
Versal Adaptive SoC CPM Mode for PCI Express Product
Guide (PG346).