Context Programming - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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  • Program all mask registers to 1. They are QDMA_IND_CTXT_MASK_0 (0x824) to QDMA_IND_CTXT_MASK_7 (0x840) .
  • Program context values on to the following registers: QDMA_IND_CTXT_DATA_0 (0x804) to QDMA_IND_CTXT_DATA_7 (0x820)
  • A host profile table context needs to be programmed before any context settings QDMA_CTXT_SELC_HOST_PROFILE. Select 0xA in QDMA_IND_CTXT_CMD (0x844), and write all data field to 0s and program context. All other values are reserved.
  • Refer to software descriptor context structure, C2H prefetch context structure and C2H CPMT context structure to program the context data registers.
  • Program any context to corresponding queue in the following context command register: QDMA_IND_CTXT_CMD (0x844).
    • Qid is given in bits [19:7].
    • Opcode bits [6:5] selects what operations must be done.
      • 0 = QDMA_CTXT_CLR : All content of context is zeroed out. Qinv is sent out on tm_dsc_sts
      • 1 = QDMA_CTXT_WR : Write context
      • 2 = QDMA_CTXT_RD : Read context
      • 3 = QDMA_CTXT_INV : Qen in set to zero and other context values are intact. Qinv is sent out on tm_dsc_sts and unused credits are sent out.
    • The context that is accessed is given in bits [4:1].
      • 4'h0 = QDMA_CTXT_SELC_DEC_SW_C2H; C2H Descriptor SW Context
      • 4'h1 = QDMA_CTXT_SELC_DEC_SW_H2C; H2C descriptor SW context
      • 4'h2 = QDMA_CTXT_SELC_DEC_HW_C2H; C2H Descriptor HW Context
      • 4'h3 = QDMA_CTXT_SELC_DEC_HW_H2C; H2C Descriptor HW Context
      • 4'h4 = QDMA_CTXT_SELC_DEC_CR_C2H; C2H Descriptor HW Context
      • 4'h5 = QDMA_CTXT_SELC_DEC_CR_H2C; H2C Descriptor HW Context
      • 4'h6 = QDMA_CTXT_SELC_WRB; CMPT / used ring Context
      • 4'h7 = QDMA_CTXT_SELC_PFTCH; C2H PFCH Context
      • 4'h8 = QDMA_CTXT_SELC_INT_COAL; Interrupt Aggregation Context
      • 4'h9 = Reserved
      • 4'hA = QDMA_CTXT_SELC_HOST_PROFILE; Host Profile Table (Only QDMA_CTXT_CMD_WR and QDMA_CTXT_CMD_RD supported)
      • 4'hB = QDMA_CTXT_SELC_TIMER; Timer Context (Only QDMA_CTXT_CMD_INV supported)
      • 4'hC = QDMA_CTXT_SELC_FMAP FMAP table write (Only QDMA_CTXT_CMD_WR and QDMA_CTXT_CMD_RD supported)
      • 4'hD = QDMA_CTXT_SELC_FNC_STS (Per function BME enable/Disable)
    • Context programing write/read does not occur when bit [0] is set. For more information on register 0x844, refer qdma_v5_0_pf_registers.csv available in the Register Reference File.