Config Block PCIE Data Width (0x18)

Config Block PCIE Data Width (0x18) - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID

PG344

Release Date

2024-11-22

Version

2.0 English

Table 1. Config Block PCIE Data Width (0x18)
Bit Index	Default	Access Type	Description
[2:0]	C_DAT_WIDTH	RO	pcie_width PCIe AXI4-Stream Width 0: 64 bits 1: 128 bits 2: 256 bits 3: 512 bits