PL PCIe GT Selection - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID

PG344

Release Date

2024-06-03

Version

2.0 English

For PL PCIE blocks the most adjacent GTs should be used and connected to the PCIe solution IP where possible. The PL PCIE block supports x1, x2, x4, x8, and x16 link widths. This provides the best place, route, and timing result for the PCIe solution.

For GTs on the left side of the device, it is suggested that, PCIe lane 0 is placed in the bottom-most GT of the bottom-most GT Quad. Subsequent lanes use the next available GTs moving vertically up the device as the lane number increments. This means that the highest PCIe lane number uses the top-most GT in the top-most GT Quad that is used for PCIe.

For GTs on the right side of the device, it is suggested that, PCIe lane 0 is placed in the top-most GT of the top-most GT Quad. Subsequent lanes use the next available GTs moving vertically down the device as the lane number increments. This means that the highest PCIe lane number uses the bottom-most GT in the bottom-most GT Quad that is used for PCIe.

Note: The implemented device view in Vivado shows lane 0 on the bottom-most GT of the bottom-most Quad on the right side of the device, but lane re-ordering is handled in logic to place lane 0 on the top-most GT of the top-most GT Quad. The GT Quad IP does not allow channel level control to remap the GT pins.

Note: The GT setting tab is not available for PL PCIE IP alone. PCIe support block must be added to include GT quad and PCIE PHY. PCIE PHY includes GT setting tab.