The Descriptor Engine stores per queue configuration, status and control
information in descriptor context that can be stored in block RAM or UltraRAM, and the
context is indexed by H2C or C2H QID. Prior to enabling the queue, the hardware and
credit context must first be cleared. After this is done, the software context can be
programmed and the qen bit can be set to enable the
queue. After the queue is enabled, the software context should only be updated through
the direct mapped address space to update the Producer Index and Interrupt
Arm®
bit, unless the queue is being disabled. The hardware context and
credit context contain only status. It is only necessary to interact with the hardware
and credit contexts as part of queue initialization to clear them to all zeros. Once the
queue is enabled, context is dynamically updated by hardware. Any modification of the
context through the indirect bus when the queue is enabled can result in unexpected
behavior. Reading the context when the queue is enabled is not recommended as it can
result in reduced performance.