Example Design - 2.0 English

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

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2.0 English

This chapter contains information about the example designs provided in the AMD Vivado™ Design Suite.

Tip: The PCIe reset pin for PL PCIE designs can be connected to any compatible single ended PL I/O pin location. If your board is compatible for either CPM4 or PL PCIE usage, you can use the CPM4 pin MIO38 to route the sys_rst_n. When this is done, the PL PCIE can use the reset as routed to the PL.
Before opening the example design, set the following Tcl property to use the reset on the MIO38 pin:
set_property CONFIG.insert_cips {true} [get_ips pcie_versal_0]